An Optimized Vertical GaN Parallel Split Gate Trench MOSFET Device Structure for Improved Switching Performance

نویسندگان

چکیده

This work proposes a vertical gallium nitride (GaN) parallel split gate trench MOSFET (PSGT-MOSFET) device architecture suitable for power conversion applications. Wherein two gates, and field plate are introduced vertically on the sidewalls connected, respectively, to source. Technology computer-aided design (TCAD) simulator was used in process achieve specific on-resistance as low 0.79 mΩ.cm 2 device, which has capacity of blocking voltages up 600 V. The peak electric PSGT-MOSFET could well be lowered 2.95 MV/cm, is about 17% lower than that conventional (TG-MOSFET) near corner with help optimization depth, drift doping, thickness. TCAD simulation shows higher doping performance produces ~2× switching losses when compared similarly rated TG-MOSFET device.

برای دانلود باید عضویت طلایی داشته باشید

برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

A Novel Dual Gate Strained-Silicon Channel Trench Power MOSFET For Improved Performance

In this paper, we propose a new dual gated trench power MOSFET with strained Si channel using the Si0.8Ge0.2 base and graded strained Si accumulation region using compositionally graded Si1-xGex buffer (x varying from 0 to 0.2 from the drift region to the base region) in drift region. We show that the introduction of strain in channel and accumulation region results in about 10% improvement in ...

متن کامل

The vertical replacement-gate (VRG) MOSFET

We have fabricated and demonstrated a new device called the vertical replacement-gate (VRG) MOSFET. This is the first MOSFET ever built in which: (1) all critical transistor dimensions are controlled precisely without lithography and dry etch, (2) the gate length is defined by a deposited film thickness, independently of lithography and etch, and (3) a high-quality gate oxide is grown on a sing...

متن کامل

Performance Analysis of Dual Gate Mosfet in Parallel Adder

This paper describes a parallel single-rail self-timed adder using dual gate MOSFETs which builds on a recursive formulation for performing multibit binary addition. Thus the addition is equivalent for those bits that do not need any carry chain propagation and the circuit attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. ...

متن کامل

Optimization of GaN Growth Conditions for Improved Device Performance

By accurately optimizing the growth conditions for an oxygen doped AlN nucleation layer and for the subsequent epitaxial process the crystal quality of our GaN could drastically be improved. In X-ray diffraction (XRD) analyses we observed FWHM values of 39 arcsec and 114 arcsec for the symmetric (004) and asymmetric (114) reflection, respectively. Consequently, the nominally undoped samples sho...

متن کامل

Performance Analysis of AlInN/GaN Underlap DG MOSFET for varying Underlap and Gate length

In this work, we investigate the performance of 18nm gate length AlInN/GaN Heterostructure Underlap Double Gate MOSFETs, using 2D Sentaurus TCAD simulation. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to large twodimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive devic...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

ژورنال

عنوان ژورنال: IEEE Access

سال: 2023

ISSN: ['2169-3536']

DOI: https://doi.org/10.1109/access.2023.3265477